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Michelle Te, I-Connect007 |
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My husband and I recently became empty-nesters (again), and it’s an interesting dynamic when you aren’t arranging your daily routines around your kids’ schedules and lives. You don’t feel as rushed, and you can turn your attention to some other things that have been put on hold, but you also feel a little melancholy about the changes, and you hope you’ve instilled enough of your wisdom into your children before they move away.
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Leo Lambert, EPTAC |
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I spent a week in Paris in September at the IPC Builds meetings, and it gave me the chance to see, take part in, and document a broad range of technical and training-related discussions affecting the electronics manufacturing industry. I go to these meetings because what gets decided in those rooms ends up in the classes we teach at EPTAC. In addition to attending committee meetings, I participated in keeping minutes for several sessions because some meeting leaders were unable to attend due to travel restrictions.
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ELIC: Every Layer Interconnect - The Promise, the Pain, and the Practical Limits - As component pitches shrink and routing density climbs, ELIC is pushing PCB fabrication into territory closer to semiconductor packaging than traditional HDI. This whitepaper explores ELIC's density advantages, manufacturing challenges, DFM pitfalls, yield considerations, and why designing to a fabricator's real process window is critical to successful production. Download now. |
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Sponsored |
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Sukanya Natarajan, Global Electronics Association |
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In July 2026, the Union Cabinet chaired by the Prime Minister approved the Semicon 2.0 for the development of India's semiconductor design and manufacturing ecosystem, with a total budget outlay of Rs. 1,27,500 crore (approximately 13.3 billion USD). With this, India could account for nearly 10% of the global semiconductor industry market in the coming years and is expected to play a much bigger role in the global semiconductor value chain, Union Minister for Electronics and Information Technology Ashwini Vaishnaw said while addressing a press briefing in New Delhi on Oct. 5.
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Will Your Vias Survive the Heat? The Printed Circuit Assembler's Guide to... Via Structures: Reflow Process Survivability, Reliability, and Robustness, the latest book from I-Connect007’s respected technical library, challenges long-held assumptions about how the electronics industry evaluates PCB via structures. Drawing on decades of experience, author Bob Neves combines technical depth with practical guidance, providing engineers and manufacturers with a roadmap for evaluating today's increasingly complex via structures with greater accuracy and confidence. Download your free copy today. |
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Director of Product Management & Technology–Asia
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